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The data center stopped being a CPU with helpers. It is now a team of specialists, and every chip on this list exists because one bottleneck got expensive enough to deserve its own silicon. Here is the whole zoo in one sitting, with the real hardware.
CPU: the generalist. Big, complex cores with deep branch prediction and generous caches. It runs anything, which is exactly why it wins nothing specialized. The 2026 flagship class, AMD's EPYC Turin, packs up to 192 cores and twelve DDR5 channels, and its most important job in an AI cluster is everything the accelerators cannot do: orchestration, storage daemons, the operating system, your control plane.
GPU: the throughput machine. Thousands of simple cores plus tensor units, fed by memory bandwidth no CPU can touch. NVIDIA's B300 carries 288 GB of HBM3e at 8 TB/s and delivers roughly 15 petaFLOPS of dense FP4. It earns its keep only when a problem parallelizes into tens of thousands of identical operations, which is precisely what training and inference are.
DPU: the infrastructure processor. The one network engineers should know best. A DPU is a NIC that grew a computer: BlueField-3 pairs sixteen Arm cores with line-rate accelerators for networking, storage, and crypto at 400 Gb/s. It runs the infrastructure, vSwitching, overlays, firewalling, NVMe-oF, on the card, so the host CPU sells its cycles to tenants instead of spending them on plumbing. In the DGX B300 system, DPUs handle the frontend while each GPU gets its own ConnectX NIC for the backend fabric.
NPU: the whisper-quiet one. A small dataflow engine for neural inference inside your laptop or phone SoC, built for milliwatts, not megawatts. Apple's Neural Engine and the 50 to 85 TOPS units in current AI PCs run the local transcription and image models without waking the fans. Same math as the big accelerators, opposite power budget.
TPU: the single-tenant heavyweight. Google's systolic-array ASIC, built for exactly one workload family: dense tensor math at pod scale. The current Ironwood generation does 4,614 FP8 TFLOPS with 192 GB of HBM3e at 7.4 TB/s, and scales to 9,216 chips in one pod over a 9.6 Tb/s inter-chip fabric. You do not buy one at retail; you rent it from Google, through Google Cloud or, new in 2026, through partner data centers.
FPGA: the shapeshifter. No fixed instruction set at all, just a fabric of lookup tables and DSP blocks you wire into whatever pipeline you need, with deterministic nanosecond latency. Today's flagships, AMD's Versal adaptive SoCs and Altera's Agilex 7, add hardened AI engines to the fabric. This is the silicon of 5G radio processing, exchange trading floors, and every prototype that later becomes an ASIC.
The whole zoo at a glance
| Optimized for | Compute model | 2026 flagship class | Where it lives | |
|---|---|---|---|---|
| CPU | Latency, generality | Few complex cores, deep speculation | EPYC Turin: 192 cores, 12ch DDR5 | Everywhere; the control plane |
| GPU | Parallel throughput | Thousands of cores + tensor units | B300: 288 GB HBM3e, ~15 PF FP4 | Training and inference nodes |
| DPU | Infrastructure offload | Arm cores + line-rate accelerators | BlueField-3: 16 cores, 400 Gb/s | The server's NIC slot |
| NPU | Inference per watt | Small dataflow MAC arrays | 50-85 TOPS client NPUs | Phone and laptop SoCs |
| TPU | Tensor math at pod scale | Systolic arrays | Ironwood: 4,614 FP8 TFLOPS, 9,216-chip pods | Google Cloud + partner clouds |
| FPGA | Reconfigurable pipelines, deterministic latency | LUT fabric + DSP + AI engines | Versal, Agilex 7 | 5G RAN, finance, prototyping |
The memory trick: name the bottleneck and the chip names itself. Single-thread latency is a CPU problem. Parallel math is a GPU problem. Infrastructure stealing host cycles is a DPU problem. Battery life is an NPU problem. Tensor math at building scale is a TPU problem. And a pipeline the vendors never imagined is an FPGA problem. One job each, and the modern data center employs all six.
Photo credits: CPU photo Getty Images via Lifewire; GPU image via GamesBap; DPU (NVIDIA BlueField) photo courtesy StorageReview; Apple M1 (CC0); TPU v4 from Jouppi et al. (CC BY 4.0); Xilinx Virtex-6 (CC BY-SA 3.0). Spec sources: AMD EPYC 9005 documentation, NVIDIA DGX B300 and BlueField-3 datasheets, Google Cloud TPU7x documentation, AMD Versal and Altera Agilex 7 product pages.
